At present, in order to improve performance of a power semiconductor device in a chip to block high voltage and reliability of the device, divider structure and the cutoff ring are typically arranged sequentially at a periphery of an active area of the power semiconductor device, and moreover, scribe line can be further arranged at the periphery of the cutoff ring, thus forming the power semiconductor device as illustrated in FIG. 1. FIG. 1 is a schematic structural diagram of the power semiconductor device in the prior art in a cross section, 11 represents the active area, 12 represents the divider structure, 13 represents the cutoff ring and 14 represents the scribe line. If the power semiconductor device is an N-type substrate, then the divider structure therein is P-type dopants, and N-type dopants in a high dosage are implanted into a periphery of the power semiconductor device, thus forming the cutoff ring as illustrated in FIG. 1.
However the cutoff ring in the prior art is fabricated by implanting ions at the periphery of the power semiconductor device, so that the cutoff ring has a greater width, resulting in occupying a considerable area of the chip, and lowering a utilization ratio of the area of the chip and consequently increasing a cost of fabricating the chip.